ASIC Verification Engineer (5082r)
Santa Clara , CA | Contract
ASIC Verification Engineer
• Perform verification of mixed-signal ASICs.
• Write, maintain and update test plans.
• Create the verification environment with scripts and makefiles.
• Write BFMs and scoreboards for logic blocks that will be verified with UVM.
• Write scripts to make it easy for other test writers to generate UVM sequences.
• Write testcases for Constrained Random Tests (CRT).
• Define functional coverage models and gather automatic coverage data with SV covergroups and coverpoints.
• Write assertion checks for critical signals.
• Write scripts to perform regression testing.
• 8 + years of experience
• In-depth knowledge of System Verilog and UVM.
• Some scripting languages such as Python, Ruby, Tcl, etc.
• In-depth Experience with writing constrained random tests. Randomization.
• Analog or mixed signal experience highly desire