Physical Design Engineer (5120r)
Mountain View, CA | Contract
Physical Design Engineer
The individual will be responsible for back-end ASIC Design including physical place and route, timing analysis, and physical verification. Successful candidates will have a thorough understanding of digital design concepts and have prior experience with ASIC development process. Must have done tape out in 40nm technology, proficient in ICC2 place and route tool, static timing analysis, and physical verification (LVS/DRC). Proficient in timing closer of DDR type interface.
• Experience in backend ASIC design including place and route, static timing analysis, physical verification (LVS/DRC).
• Experience with Synopsys ASIC toolset specifically Synopsys ICC2
• Experience in timing closer of DDR interface , balancing data and clock paths for high frequency design
• Proficiency in scripting languages such as Tcl, Python or Perl
• Experience in 40nm technology node. Experience with TSMC Foundries
• Mentor Calibre LVS/DRC tool
• Mixed signal or analog experience is a big plus. Team will interface with analog team.