ASIC Verification Engineer - PCIe, DDR interfaces
DOE Mountain View, CA 94043 | Contract
Block level verification of PCIe and DDR memory controllers for ASIC.
Install PCIe and DDR verification IPs. Run compliance tests with IP and integrate into full chip test bench. Run full chip simulation with SystemVerilog.
- Experience verifying PCIe and DDR interfaces - must have experience with PCIE gen 3 or later and DDR gen 3 or 4.
- Previous experience using VIPs for PCIe and DDR
- VIPs such as Cadence Denali or Avery
- C++ not required but would be additional benefit